In recent several years, ASIC (Application Specific Integrated Circuit) technology has evolved from a chip-set philosophy to an embedded cores based system-on-a-chip (SoC). An SoC is an IC designed by stitching together multiple stand-alone VLSI designs (cores) to provide full functionality for an application. Namely, the SoCs are built using pre-designed models of complex functions known as “cores” (also known as Intellectual Property or IP) that serve a variety of applications. These cores are generally available either in high-level description language (HDL) such as in Verilog/VHDL (known as soft-cores), or in transistor level layout such as GDS II (known as hard-cores) An SoC may contain combinations of hard and soft cores for on-chip functions such as microprocessors, large memory arrays, audio and video controllers, modem, internet tuner, 2D and 3D graphics controllers, DSP functions, and etc.
After the design stage conducted under EDA (electronic design automation) environment, the SoC design is implemented in the form of a silicon chip. This invention is directed to a methodology for evaluating the SoC design in the form of silicon (“silicon debug”) for each of the cores in the SoC. While such system-chips serve for broad applications, the complexity of these chips is far too complex to be tested by conventional means. (“Testing embedded cores” A D&T Roundtable, IEEE Design and Test, pp. 81-89, April-June 1997, “Challenge of the 90's Testing CoreWare based ASICs” Panel on “DFT for embedded cores”, R. Rajsuman, International Test Conference, pp. 940, 1996).
In addition to the difficulties in the production testing, these SoCs also present major difficulty in determining their functional correctness when prototype silicon is manufactured. The primary cause of the difficulty is limited observability and controllability of individual cores. In general, only the chip I/Os (input and output of SoC chip) are accessible to apply a test vector or to observe a response to the test vector while I/Os of each embedded core is not accessible. Thus, in a complex SoC, many internal faults do not show-up at the chip I/Os.
FIG. 1 illustrates an example of general structure of SoC 10 that has an embedded memory 12, a microprocessor core 14, and three function-specific cores 16, 18 and 20, PLL (phase lock loop) 22 and TAP (test access port) 24. The overall testing of SoC can be done only through the chip-level I/Os. In this example, such chip level I/Os are established as chip I/O pads 28 formed on an I/O pad frame 26 at the outer periphery of SoC 10. Each of the functional cores 12, 14, 16, 18 and 20 includes a pad frame 29 which is typically contains multiple I/O pads of cores at core periphery. Generally, in IC design, the top metal layer is used for only power pads 32 for power sources while intermediate metal layers are used for I/O or signal pads for interfacing with other cores, microprocessor core and embedded memory.
In case of a failure, it is extremely important to know the cause of failure, such as if it is due to the microprocessor core 14 or the function specific cores 16, 18 or 20, or other causes. The reason that debugging the failure is necessary is that the failure must be corrected before the SoC design is sent to mass production.
To debug the failure, it is extremely desirable that the individual I/Os of each core are accessible so that core specific test patterns can be applied. At the present time, IEEE P1500 working group is developing a solution so that core I/Os become accessible. This solution is based upon use of extra logic that includes a shift-register based wrapper at the core I/Os and a data transport bus from chip I/Os to core I/Os (“Preliminary outline of the IEEE P1500 scalable architecture for testing embedded cores”, IEEE VLSI Test Symposium, 1999). This structure is illustrated in FIGS. 2A-2C where FIG. 2A shows an overall wrapper structure at the outer boundary of the core and FIGS. 2B and 2C respectively show structures of input cell 42 and output cell 44 in the wrapper of FIG. 2A.
Similar solutions based upon core wrapper and data transport logic have also been proposed by the Virtual Socket Interface Alliance (VSIA) and other researchers (Manufacturing related test development specification 1”, version 1.0, VSI Alliance, 1998, “Test access architecture” VSI Alliance, 2000, and “Hierarchical test access architecture for embedded cores in an integrated circuit”, D. Bhattacharya, IEEE VLSI Test Symposium, pp. 8-14, 1998).
The major drawbacks in these methods are that they require extra logic that increases chip size and hence the cost; and performance penalty because of the wrapper at the core I/Os. An example of such performance penalty includes signal propagation delays in SoC because of the additional circuit components and paths. Also, in all cases, a test vector is shift-in the wrapper register and response is shifted-out using multiple clock cycles. Until the response of previous vector is completely shifted-out, a new test vector cannot be applied. Hence, in all these solutions, testing time become too long and at-speed testing of core cannot be done. This also means that timing related failures cannot be debugged with these solutions.
Another conventional approach is a “bed of nails” type method described in U.S. Pat. Nos. 4,749,947 and 4,937,826. In this method, a grid of wires is created on which the functional circuit to be tested is placed. Every node in the functional circuit can be accessed by a vertical transistor that can provide connection from node to the grid-wires. In principle, this method provides 100% observability. However, this method is extremely expensive as it requires multiple additional steps (layout masks) and modification in the existing manufacturing process of SoC. Also, because of the presence of grid of wires, it significantly increases circuit parasitic capacitance and results in performance penalty.
As in the foregoing, the conventional technologies are not satisfactory for fully debugging individual core in SoC without drawbacks such as increasing the size and cost or involving the performance penalty.